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    • 专利摘要:
    A method of making a structure comprising one or more strained semiconductor regions capable of respectively forming one or more transistor channel regions, the method comprising the steps of: a) providing a substrate (1) ) coated with a masking layer (3) having one or more first slots (4a) respectively revealing one or more first oblong semiconductor portion (s) (6a) in a first semi material -conductor (5) and extending in a first direction, b) growing a second semiconductor material (7) having a mesh parameter different from that of the first semiconductor material (5), so as to form on said one or more first oblong semiconductor portions (6a): one or more first constrained semiconductor blocks (18a) in the first direction.
    公开号:FR3048815A1
    申请号:FR1652112
    申请日:2016-03-14
    公开日:2017-09-15
    发明作者:Emmanuel Augendre；Nicolas Loubet；Sylvain Maitrejean；Pierre Morin
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；STMicroelectronics lnc USA；
    IPC主号:
    专利说明:

    METHOD FOR CO-REALIZATION OF ZONES UNDER DIFFERENT UNIAXIAL CONSTRAINTS
    DESCRIPTION
    TECHNICAL FIELD AND PRIOR ART
    The present application relates to the field of structures comprising a semiconductor layer having a deformation or a mechanical stress, and applies in particular to the production of transistors having a constrained channel structure.
    By mechanical deformation is meant a material which has its parameter (s) of elongated crystalline mesh (es) or shortened (s) with respect to a nominal mesh parameter.
    In the case where the deformed mesh parameter is larger than the so-called "natural" parameter of the crystalline material, it is said to be in tension. When the deformed mesh parameter is smaller than the natural mesh parameter, the material is said to be in compression.
    A mechanical stress in tension or in compression on a semiconductor layer makes it possible to induce an increase in the speed of the charge carriers. This improves the performance of transistor devices formed in such a layer.
    A common example of constrained structure is formed of voltage-grown silicon obtained by epitaxial growth on a plastically relaxed SiGe buffer layer or SiGe-based compression in epitaxial compression or by a Germanium enrichment process on silicon.
    The aforementioned techniques give rise to bi-axial mechanical stresses in the plane.
    The fact of having a semiconductor layer with biaxial mechanical stress has the disadvantage that, when active zones of different widths are produced, an elastic relaxation by the edges takes place and the average stress, the mobility and the density of the current are dependent on the width of these areas.
    Moreover, a compressive stress is even more beneficial to the transport of holes that it is uni-axial. Likewise, above 1.4 GPa, a stress in tension is all the more beneficial to electron transport because it is uni-axial.
    In the document: "A mobility enchancement strategy for sub-14nm power-efficient FDSOI technologies" by DeSalvo et al., Narrow-band constrained semiconductor zones are cut in order to obtain a relaxation in a direction transverse to that wherein the strips extend.
    The problem arises of finding a new method making it possible to produce one or more semiconductor zones that are stresses on a substrate, and in particular semiconductor zones in uniaxial stress.
    STATEMENT OF THE INVENTION
    An embodiment of the present invention provides a method for producing a structure comprising one or more constrained semiconductor regions or constrained semiconductor blocks capable of respectively forming one or more transistor channel regions. the method comprising steps of; a) providing a substrate coated with a masking layer having one or more first slots respectively revealing one or more first semiconductor portion (s) oblong (s) in a first semiconductor material and which s extend in a first direction, b) growing a second semiconductor material having a mesh parameter different from that of the first semiconductor material, so as to form on said one or more first oblong semiconductor portions: one or more several first semiconductor blocks constrained in the first direction.
    Due to the oblong shape of the semiconductor portions on which growth is carried out, relaxation takes place in a direction orthogonal to the first direction.
    In order to obtain an elastic relaxation of the first semiconductor block or blocks, the first oblong semiconductor portions advantageously have: a width Wi less than 4 times the critical plastic relaxation thickness hc of the second semiconductor material, and or a length U of at least 20 times the critical thickness of plastic relaxation hc of the second semiconductor material.
    According to one possible implementation of the method, in step b), at least one of said first semiconductor blocks can be formed by growth of a semiconductor strip on a given first oblong semiconductor portion extending in the first direction and another semiconductor strip on another first oblong semiconductor portion extending in the first direction, said semiconductor strips joining to form a first semiconductor block, said first semiconductor block a conductor being arranged facing said given first oblong semiconductor portion and said other first oblong semiconductor portion and a masking band belonging to the masking layer and separating said given first oblong semiconductor portion from said another first oblong semiconductor portion.
    With such an arrangement, the relaxation effect is increased in a direction orthogonal to the first direction. It tends to form a first semiconductor block with a uni-axial stress in the first direction.
    To obtain a better elastic relaxation in a direction orthogonal to the first direction, the masking band separating said first oblong semiconductor portion given from said other first oblong semiconducting portion advantageously has a width less than the critical thickness of plastic relaxation hc of the second semiconductor material.
    Advantageously, the second semiconductor material is formed by isotropic growth by epitaxy. This makes it possible to minimize the appearance of crystalline defects.
    According to one possible implementation of the method, in step a) the masking layer may be provided with one or more second slot (s) respectively revealing one or more second (s) portion (s) semi-conductor (s) ( s) oblong (s) based on the first semiconductor material and which extend in a second direction, orthogonal to the first direction, step b) comprising the growth of the second semiconductor material on said one or more second (S) oblong semiconductor portion (s) so as to form at least one second semiconductor block constrained in the second direction.
    The second semiconductor material may be provided with respect to the first semiconductor material so that their differences in respective mesh parameters result in a first semiconductor block and a second semiconductor block constrained in compression. The method may then further comprise, after step b), a step of growth of a given semiconductor material on the second semiconductor block, the given semiconductor material having a mesh parameter different from that of the second semiconductor material so as to form a voltage-constrained semiconductor region on the second semiconductor block. In this case, this makes it possible to form a first block constrained in compression and a second block covered with a voltage-stressed region.
    The second semiconductor material may for example be based on Sii-xGex (with x> 0) while the given semiconductor material is silicon. The first semiconductor material may also be silicon.
    The method may further comprise, after step b), a step of growing the second semiconductor material on the first semiconductor block.
    It is thus possible to raise the first block so preferably that it is substantially at the same height as the second semiconductor block.
    After forming said first semiconductor block and said second semiconductor block, the first semiconductor block and said second semiconductor block can be covered respectively with a first semiconductor region and a second semiconductor region. . In this case, the method may further comprise, after formation of the first semiconductor region and / or the second semiconductor region, the implementation of at least one gate on the first semiconductor region and / or on the second semiconductor region.
    The method may further comprise, after step b), steps of: - formation of an insulating layer on the first semiconductor block and on the second semiconductor block, - bonding of the insulating layer on a support - removal of said substrate.
    According to an implementation possibility for which after formation of the first block and the second semiconductor block, the first semiconductor block and the second semiconductor block are covered respectively with a first semiconductor region and a first semiconductor block. second semiconductor region, the method may further comprise, after removal of the substrate, an etching of the first semiconductor block and the second semiconductor block so as to respectively reveal the first semiconductor region and the second semiconductor region. .
    It is thus possible to form a semiconductor-on-insulator structure and in particular to have a voltage-constrained semiconductor region and a semiconductor region constrained in compression on the insulating layer of the support.
    Prior to forming the first semiconductor region, an etch stop layer may be formed on said first semiconductor block, said etch stop layer being based on the first semiconductor material. This facilitates the etching step of unveiling the first region and the second semiconductor region.
    After having unveiled the first semiconductor region and the second semiconductor region, it is possible to complete the formation of transistors and in particular to realize one or more transistor gates on the first semiconductor region and the second semiconductor region. conductive.
    According to a possibility of implementing the method, after formation of said one or more first semiconductor blocks, a stack is formed on the first semiconductor block comprising an alternation of bars based on a given semiconductor material and the second semiconductor material.
    According to one possible embodiment, the method may comprise steps of: - forming an insulating mask on the first semiconductor block, the insulating mask being provided with one or more holes facing respectively one or more first oblong semiconductor portion (s), - forming semiconductor bars in said one or more holes, by growth of the second semiconductor material or of a given semiconductor material having a parameter of mesh different from that of the second semiconductor material. Such an embodiment can be used for the implementation of devices finFET type.
    BRIEF DESCRIPTION OF THE DRAWINGS
    The present invention will be better understood on reading the description of exemplary embodiments given, purely by way of indication and in no way limitative, with reference to the appended drawings in which: FIGS. 1A-1L illustrate an exemplary method for producing at least one semiaxial region constrained in uniaxial compression and at least one semiaxial voltage-constrained semiconductor region on the same substrate; FIG. 2 illustrates an example of a particular arrangement of a transistor gate formed on a semiconductor block constrained according to a uniaxial stress and resulting from the meeting of two semiconductor regions; FIGS. 3A-3C illustrate an example of implementation of finFET transistors, respectively, with a uni-axial voltage constrained channel structure and with a channel structure constrained in uniaxial compression; FIGS. 4A-4D illustrate an example of a method in which, after forming a semiaxial region constrained in uniaxial compression and a semiaxial region constrained in uni-axial tension on the same substrate, these regions are transferred to another support so as to achieve a constrained semiconductor structure on insulator; FIGS. 5A-5B illustrate an embodiment of transistors respectively on a semiaxial constrained semiconductor region and a uni-axial voltage-constrained semiconductor region; FIGS. 6A-6B illustrate an embodiment of channel structure transistors formed of superimposed and constrained semiconductor bars;
    Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the passage from one figure to another.
    The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable.
    In addition, in the following description, terms such as "superior" which depend on the orientation of the structure apply considering that the structure is oriented as illustrated in the figures.
    DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
    An example of a method for producing a constrained semiconductor block in uniaxial compression and a semiaxially constrained semiconductor block on the same support, will now be given in conjunction with FIGS. IL.
    The starting material of this process may be a surface layer 1 of a bulk substrate ("bulk" according to the English terminology) or a semiconductor-on-insulator type substrate. The surface layer is made of a semiconductor material, for example silicon, in particular monocrystalline material.
    On the substrate 1, a layer 3 is first formed in a material intended to serve as masking for epitaxial growth. This layer 3 may be made of an amorphous and typically insulating material such as, for example, silicon nitride or, advantageously, silicon oxide. In the case where the layer 3 is oxide, it is made for example by growth or by deposition.
    In the masking layer 3, then narrow and narrow openings are also formed, also called "slots" 4a, 4b, for example by photolithography and etching of the masking layer 3.
    Among the slots 4a, 4b there are one or more first slots 4a which extend in a first direction parallel to the main plane of the substrate 1, and one or more second slots 4b extending thereto. ) in a second direction, both parallel to the main plane of the substrate 1 and orthogonal to the first direction.
    By "main plane" of the substrate 1 is meant here and throughout the description a plane passing through the substrate 1 and which is parallel to the plane [O; x; y] orthogonal reference [O; x; y; z] given in Figure IB.
    In the example of FIG. 1B, the first and second directions are parallel respectively to the y-axis and the z-axis of the orthogonal reference [O; X; y; z]. The slots 4a, 4b typically have a rectangular shape with a length much greater than their width, for example at least 10 times greater than their width.
    Next, a first semiconductor material is grown on one or more semiconductor region (s) of the substrate disclosed respectively by the first slot (s) 4a and on one or more several regions of the substrate unveiled by the second slot (s) 4b. The first slots 4a can be made with respect to a region dedicated to the production of at least one transistor of a first type, for example of the P type, while the second slots 4b are in this case made with respect to another region dedicated to producing at least one transistor of a different type, for example of type N.
    Thus, in a first slot 4a and in a second slot 4b, a first oblong semiconductor portion 6a and a second oblong semiconductor portion 6b based on the first semiconductor material 5 are formed (FIG. 1C giving a sectional view transverse A'A and figure ID giving a view from above of the structure). The first semiconductor material 5 may be similar to that of the substrate on which it is formed, for example silicon. The growth of the oblong portions 6a and 6b can be made such that these oblong portions 6a, 6b reproduce the shape of the slots 4a, 4b. The oblong semiconductor portions 6a and 6b are preferably arranged so that their upper face is situated substantially at the same level as the upper face of the masking layer 3. By "substantially the same level" is meant that the oblong semiconductor portions 6a and 6b are at the same level or protrude from the upper face of the masking layer 3, preferably at most 5 nm.
    Then, on the oblong semiconductor portions 6a, 6b revealed by the masking, a second semiconductor material 7 is grown having a mesh parameter different from that of the first semiconductor material 5. The second semiconductor material is for example Silicon Germanium (Sii-xGex), especially when the first semiconductor material is silicon. The second semiconductor material 7, also called "buffer" material, is in mesh disagreement with the first semiconductor material 5, is formed by epitaxial growth.
    In the case of growth of SiGe, the growth is preferably carried out at a temperature below 600 ° C. and under an inert atmosphere, for example of N 2.
    Preferably, the dimensions of the slots 4a, 4b, and consequently those of the oblong semiconductor portions 6a, 6b, are provided, depending on the nature of the second semiconductor material 7 and the associated critical plastic relaxation thickness hc. of this material. The critical thickness hc is defined as the thickness below which the material grows without dislocation and is evoked in the document entitled "Critical thickness for plastic relaxation of SiGe" by Hartmann et al. Journal of Applied Physics 2011.
    For example, the document "Si / SiGe heterostructures: from material and physics to devices and circuits" by DJ Paul, semi-conductor Science and Technology, makes it possible to give a critical thickness estimate as a function of the Germanium x concentration of the second semiconductor material 7 when it is silicon germanium (Sii-xGex). In the present case, the critical thickness is estimated in the "metastable" part of the graph of FIG. 4. The thickness e2 of the second semiconductor material 7 that is grown is preferably chosen to be smaller than the thickness Hc critical relaxation and preferably such that e2 <hc / 2.
    The epitaxial conditions of the second semiconductor material 7 are advantageously chosen so as to achieve isotropic growth, in order to limit the creation of crystalline defects and to obtain a substantially flat top surface. In particular, low temperature growth, for example less than 600 ° C., is carried out for SiGe in order to minimize differences in growth rate along the different crystalline directions. To promote isotropic growth, it is also possible to carry out this growth in the gas phase by using a neutral gas such as N 2 as a carrier gas (also called a propellant gas), in order to avoid hydrogen adsorption.
    Because of the configuration of the oblong semiconductor portions 6a, 6b, the second semiconductor material 7 tends to adopt the mesh parameter of the first semiconductor material 5 in the plane and in particular in the respective longitudinal direction of the portions. oblong semiconductors 6a, 6b in other words in the respective longitudinal direction of the slots 4a, 4b. Thus, on a first oblong semiconductor portion 6a based on the first semiconductor material 5, a first semiconductor band 8a is formed based on the second semiconductor material 7 which follows the mesh parameter of the first semiconductor material. conductor 5 in said first direction (direction parallel to the y-axis in FIG IF), while on a second oblong semiconductor portion 6b is formed a second semiconductor strip 8b based on the second semiconductor material 7 which follows the mesh parameter of the first semiconductor material 5 in said second direction (direction parallel to the x-axis in FIG. By virtue of the arrangement of the oblong semiconductor zones 6a, 6b, in the case where the second semiconductor material 7 is silicon germanium, the semiconductor strips 8a are in compressive stress (symbolized by arrows Fl in FIG. IF) in the first direction and relaxed in the second direction (arrows F'I), while the semiconductor strips 8b are in compressive stress (arrows F2) in the second direction and relaxed in the first direction (arrows F'2). ).
    In order to minimize the plastic relaxation and to be able to obtain an effective elastic relaxation and to maintain a uni-axial stress in an orthogonal direction (the uniaxial stress being in the first direction for the strips 8a and in the second direction for the strips 8b), provision is advantageously made for slits 4a, 4b of respective widths Wi (measured parallel to the x-axis for a first slot 4a) and W2 (measured parallel to the y-axis for the second slot 4b) such that Wi <4 x hc and W2 <4 x hc and respective lengths U (measured parallel to the y-axis for a first slot 4a) and L2 (measured parallel to the x-axis for a second slot 4b) such that U> 20 x hc and L2> 20 x hc, with hc the critical thickness of plastic relaxation mentioned above. Similarly, it is possible to provide a spacing Δ between slots 4a (or 4b) parallel to each other such that 2xhc> Δ in order to obtain the junction of the material regions 7 situated on adjacent slits (4a and 4b, for example) before their relaxation. plastic. The fact of choosing such spacing Δ slots is to ensure that regions 18a and 18b are formed before the material relaxes plastically. A junction of the zones coming from the slits 4a and 4b is then used before relaxation.
    The growth of the second semiconductor material 7 can be provided in such a way that a plurality of parallel semiconductor strips 8a made respectively from parallel and juxtaposed oblong semiconductor portions 6a join to form a first semiconductor block 18a such as as illustrated in Figures IG and IH. Similarly, semiconductor strips 8b respectively from oblong semiconductor portions 6b located side by side and extending in the second direction, are likely to meet to form a second semiconductor block 18b.
    In the example of FIGS. 1G and 1H, the semiconductor blocks 18a, 18b extend opposite parallel oblong semiconductor portions and at least one band of the masking layer 3 separating two oblong semiconductor portions. parallel.
    The semiconductor blocks 18a, 18b thus formed respectively have a compressive uni-axial stress in the first direction (arrows F1) and a compressive uni-axial stress (arrows F2) in the second direction. The first semiconductor block 18a may be dedicated to the production of at least one PMOS type transistor, while the second semiconductor block 18b, disjoint from the first block 18a, is intended to form a channel region of at least least one NMOS type transistor.
    Then, a region 24 of semiconductor material 25 on the second semiconductor block 18b having a mesh parameter different from that of the second semiconductor material 7 (FIGS. 11 and 11) can be grown by epitaxy. The difference in the mesh parameter between the semiconductor materials 7 and 25 is such that the given semiconductor material 25 which is grown on the second semiconductor block 18b in uni-axial compressive stress is then stressed in tension. uni-axial (symbolized by arrows F3 in Figure 11) directed parallel to the first direction. The given semiconductor material 25 is for example made of silicon when the second semiconductor material 7 is silicon germanium. To minimize the relaxation of the region 24, its thickness is expected to be less than a limiting thickness. In the case of a silicon layer 25 on a second 20% SiGe semiconductor block 18b, this limiting thickness may for example be of the order of 12 nm.
    To prevent a growth of the given semiconductor material 25 on the first semiconductor block 18a, it can be covered with a masking area for example based on silicon oxide or silicon nitride. After epitaxy, the masking used to protect the first block 18a is then removed.
    In order to raise the first block 18a relative to the second block 18b, and preferably to make blocks 18a, 18b of similar heights, an additional layer 28 of the second semiconductor material 7 may be formed by epitaxial growth. To prevent growth of the second semiconductor material 7 on the second semiconductor block 18b, it can then be covered with a masking area for example based on silicon oxide or silicon nitride. After epitaxy, the masking used to protect the second block 18b is then removed.
    There is thus a first block 18a coated with a surface region 27 constrained in uniaxial compression and a second block 18b coated with a surface region 24 stressed in uniaxial tension. The voltage constrained region 24 is favorable for accommodating at least one NMOS transistor channel region while the compression-stressed region 28 is favorable for providing at least one PMOS channel channel region. The order in which the regions 24 and 28 are made may be the opposite of the one just described.
    It is then possible to complete the formation of transistors, in particular by forming one or more grids Sla, 31b respectively on the first block 18a and on the second block 18b. The grids Sla, 31b are preferably arranged to extend in a direction orthogonal to that of the respective uni-axial stresses of the regions 24, 28 (Figure IK and Figure IL).
    The realization of the transistors may also be completed by steps of formation of insulating spacers on either side of the grids, source and drain regions, and contact formation (steps not shown).
    Advantageously, provision is made to arrange the grid or grids in a zone remote from that where the semiconductor strips 8a have met to form the first block 18a. Similarly, the gate or gates of one or more N-type transistors are arranged in a zone remote from that where the semiconductor strips 8b have met to form the second block 18b, the meeting zones being zones where Possible crystalline defects are likely to be created. In the example illustrated in FIG. 2, grids Sla are formed opposite the oblong semiconductor portions 6a having served as a growth support, in other words facing the slots 4a, while a zone where the recrystallization fronts meet. is shown schematically using a dotted line Zi.
    According to a variant of the method illustrated in FIGS. 3A-3C, it is possible to produce finFET transistors of different types and having constrained channel regions according to constraints of different natures on the same support.
    For this purpose, it is possible, for example, to start from a structure as described in connection with FIGS. 1G and 1H, comprising a first semiconductor block 18a, and a second semiconductor block 18b disjoint from the first semiconductor block 18a.
    An insulating mask 33, for example based on silicon oxide covering the semiconductor blocks 18a and 18b, is then produced. The insulating mask 33 may be arranged to extend in a space 35 separating the semiconductor blocks 18a, 18b.
    Holes are provided in the insulating mask 33, and reveal portions respectively of the first semiconductor block 18a and the second semiconductor block 18b on which semiconductor bars 38a, 38b are grown, for example of parallelepipedal shape and based on the second semiconductor material 7, for example Silicon Germanium. The holes and exposed portions of the semiconductor blocks 18a, 18b may be located in particular opposite the slots 4a, 4b.
    In an area situated above the upper face of the insulating mask 33, it is then possible to extend the bar or bars 38b located on the second block 18b by semiconductor regions 48b. These regions 48b are formed by epitaxial growth of a given semiconductor material 25, typically silicon, having a mesh parameter different from that of the second semiconductor material 7, and in particular adapted so that when it believes in the second semiconductor material 7 uni-axial compressive stress, this material 25 is then constrained in uniaxial tension. The regions 48b made on the second block 18b may also have the shape of parallelepiped bars.
    In the case where the regions 48b are in the form of parallelepipedal Si bars made on SiGe bars 38b serving as a channel for FinFET type devices, the thickness of the regions 48b is preferably less than 50 nm. Upon epitaxial growth of the regions 48b, the first block 18a may be masked to prevent growth of the given semiconductor material 25 opposite the first semiconductor block 18a. This mask can then be removed.
    As illustrated in FIG. 3A, it is also possible to extend the bar or bars 38a located on the first block 18a by regions 48a formed by growth of the second semiconductor material 7. During the growth of the regions 48a by epitaxy, the second block 18b can be protected by a temporary mask.
    The semiconductor regions 48a are provided to form channel regions of at least one P-type transistor, while the semiconductor regions 48b are able to form channel regions of at least one N-type transistor. One or more blocks 51 of coating grids are then produced on regions 48a, 48b (FIG. 3B).
    For this, steps of deposition of gate dielectric and then of gate material followed by etching of these materials are carried out.
    In the exemplary arrangement of FIG. 3C, the gate blocks 51 are common to the compression-stressed semiconductor regions 48a and the voltage-stressed semiconductor regions 48b, the gate blocks 51 extending orthogonally to these latest.
    According to a possible embodiment, it may be desired to transfer the semiconductor region (s) in uniaxial strain (s) that has been formed (for example by implementing a method as described previously in connection with Figures II-IJ) on another substrate.
    This transfer can be carried out in particular when it is desired to arrange these semiconductor regions on a semiconductor-on-insulator structure, and in particular when it is desired to arrange the semiconducting semiconductor region or regions ( s) on a thin insulating zone, for example to make a device in FDSOI technology (for "Fully Depleted Silicon Insulator") and / or UTBB (for "Ultra-Thin Body and Box").
    An exemplary embodiment of such a transfer is illustrated in FIGS. 4A-4D.
    It is possible, for example, to start from a structure as described in connection with FIGS. 1G and 1H with a first semiconductor block 18a, and a second semiconductor block 18b disjoint from the first semiconductor block 18a, and then form the regions semiconductors 28, 24 respectively on the first block 18a and on the second block 18b and which are respectively uniaxial strain stress and uniaxial compression stress.
    To facilitate removal of the donor structure, provision may be made to coat the first semiconductor block 18a with an etching stop layer 61. The etch stop layer 61 is based on the same material as the semiconductor region 24, in particular silicon.
    This barrier layer 61 is interposed between the first block 18a and the semiconductor region 28 of compression-constrained semiconductor material in which at least one transistor channel region is provided (FIG. 4B). The etching stop layer 61 is preferably of small thickness, for example less than 5 nm.
    Next, an insulating layer 63 is formed, for example based on silicon oxide covering the semiconductor zones 28, 24. In the embodiment of FIG. 4B, the insulating layer 63 extends between the semi-conducting regions -conductors 24, 28 and forms an insulating separation between these regions 24, 28.
    Insulating layer 63 may serve as a bonding layer for direct bonding to another substrate 66 (Figure AC). The other substrate 66 is semiconductor and may for example be based on silicon and optionally coated with an oxide layer. To facilitate bonding, a polishing step (CMP for "Chemical Mechanical Polishing / Planarization") of the insulating layer 63 can be performed.
    Then, the starting substrate 1 is removed, for example by grinding and then chemical etching, for example using TMAH, in particular when the substrate 1 is of bulk and silicon type.
    A layer for stopping the etching can be formed in the substrate 1 by doping, for example using Boron. The masking layer 3 based on oxide or nitride is also removed, then the blocks 18a, 18b based on the second semiconductor material 7. When these blocks 18a, 18b are based on Silicon Germanium, an etching, for example using a mixture of HF: H202: CH3C00H can be implemented. The etching is stopped when reaching the etching stop layer 61 and the semiconductor region 24 typically made of silicon.
    A structure is thus obtained as illustrated in FIG. 4D having a compression-constrained semiconductor zone 28 and a voltage-constrained semiconductor zone 24 resting on the insulating layer 63 of the substrate 66. From FIG. such a structure, one or more transistors can be realized, and in particular at least one NFET type transistor on the semiconductor region 24 and at least one PFET type transistor on the semiconductor region 28.
    FIGS. 5A-5B illustrate an embodiment of gate electrodes 81 on the semiconductor regions 24, 28 in which transistor channel regions are provided.
    The production of constrained semiconductor regions for NFET and PFET transistors, in particular in FDSOI technology, or of finFET type, has previously been described by way of example.
    A method according to the invention can be adapted to the implementation of different arrangement transistors or architectures. For example, nano-wire transistors or semiconductor rod stack transistors can be manufactured.
    In the example illustrated in FIGS. 6A-6B, one or more first semiconductor structure (s) 78a formed of a stack comprising an alternation of bars or layers (s) ) based on the second semiconductor material 7, in particular Germanium Silicon (Sii-xGex), and on layers of the given semiconductor material 25, in particular silicon, with a mesh parameter different from that of the second semi-conducting material. conductor 7. On the same support as the first structure or structures 78a, then one or two first semiconductor structure (s) comprising a stack of bars or layer (s) with an alternation of layers based on the second semiconductor material 7, and layers of the given semiconductor material 25.
    A first structure 78a alternating layers or stacked semiconductor bars can be formed from a device as illustrated in FIGS. IC-ID, in particular by performing a succession of epitaxial growths from a zone oblong semiconductor 6a. The alternating second structure 78b of stacked semiconductor layers or bars may also be formed from an oblong semiconductor region 6b.
    As for the realization of the semiconductor regions 24, 28 described above, the order with which the structures 78a, 78b are made can be reversed. One or the other of the exemplary embodiments have been given mainly with as second semiconductor material 7: silicon germanium (Sii-xGex) and as given semiconductor material 25: silicon.
    A method implemented according to the invention may provide to use other pairs of semiconductor materials having a mesh cleavage, preferably reduced and typically less than 3%. For example, it may be provided to form a first semiconductor region or semiconductor structure constrained to SixCi-x, on the same support as a second region or Si-constrained semiconductor structure. According to another example, the first region or semiconductor structure is in Ge and on the same support as a second region in GexSnl-x.
    According to another example of pairs of materials, it is possible, for example, to provide a substrate 1 based on InP and as a second semiconductor material 7 of rinxGai-xAs with 0.13 <x <0.53 which is grown on InP.
    权利要求:
    Claims (16)
    [1" id="c-fr-0001]
    A method of making a structure comprising one or more strained semiconductor regions capable of respectively forming one or more transistor channel regions, the method comprising the steps of; a) providing a substrate (1) coated with a masking layer (3) having one or more first slots (4a) respectively revealing one or more oblong first semiconductor portions (s) ( 6a) into a first semiconductor material (5) and extending in a first direction, b) growing a second semiconductor material (7) having a different mesh parameter from that of the first semiconductor material (5). ), so as to form on said one or more elongated first semiconductor portions (6a): one or more first constrained semiconductor blocks (18a) in the first direction.
    [2" id="c-fr-0002]
    2. Method according to claim 1, wherein the one or more oblong semiconductor portions (6a) have: a width (W1) less than 4 times the critical plastic relaxation thickness (hc) of the second semiconductor material (7), - a length (Ll) of at least 20 times the critical plastic relaxation thickness (hc) of the second semiconductor material (7).
    [3" id="c-fr-0003]
    3. Method according to one of claims 1 or 2, wherein in step b), at least one of said first semiconductor blocks (18a) is formed by growth of a semiconductor strip (8a) on a first given oblong semiconductor portion (6a) extending in the first direction and another semiconductor band (8a) on another first oblong semiconductor portion (6a) extending in the first direction, said semiconductor strips joining together to form a first semiconductor block (18a), the first semiconductor block (18a) being arranged opposite said given first oblong semiconductor portion (8a) and said other first semi-conductor portion (18a); -conductor oblong (8a) and a masking tape belonging to the masking layer (3) and separating said first oblong semiconductor portion given said other first oblong semiconductor portion.
    [4" id="c-fr-0004]
    The method of claim 3, wherein said masking tape separating said given first oblong semiconductor portion (8a) from said other first oblong semiconductor portion (8a) has a width (Δ) less than the critical thickness. plastic relaxation device (hc) of the second semiconductor material (7).
    [5" id="c-fr-0005]
    5. Method according to one of claims 1 to 4, wherein the second semiconductor material (7) is formed by isotropic epitaxial growth.
    [6" id="c-fr-0006]
    6. Method according to one of claims 1 to 5, wherein in step a) the masking layer (3) is provided with one or more second slot (s) (4b) respectively revealing one or more second ( s) oblong semiconductor portion (s) (6b) based on the first semiconductor material (5) and extending in a second direction, orthogonal to the first direction, step b) comprising growing the second semiconductor material (7) on said one or more second oblong semiconductor portion (s) (6b) so as to form at least one second constrained semiconductor block (18b ) according to the second direction.
    [7" id="c-fr-0007]
    The method according to claim 6, wherein the mesh parameter of the second semiconductor material (7) with respect to that of the first semiconductor material (5) is such that the first semiconductor block (18a) and the second semiconductor block (18b) are constrained in compression, the method further comprising, after step b), a step of growing a given semiconductor material (25) on the second semiconductor block (18b ), the given semiconductor material (25) having a mesh parameter different from that of the second semiconductor material (7) so as to form a voltage-constrained semiconductor region (24) on the second semiconductor block (18b).
    [8" id="c-fr-0008]
    The method of claim 7, wherein the second semiconductor material (7) is based on Sii-xGex (with x> 0) and the given semiconductor material (25) is silicon.
    [9" id="c-fr-0009]
    9. Method according to one of claims 7 or 8, wherein the method further comprises, after step b), a step of growing the second semiconductor material (7) on the first semiconductor block (18a). ).
    [10" id="c-fr-0010]
    10. Method according to one of claims 7 to 9, wherein after forming the first block (18a) and the second block (18b) semiconductor, the first semiconductor block (18a) and the second semiconductor block (18b) are respectively covered with a first semiconductor region (28) and a second semiconductor region (24), the method further comprising after forming the first semiconductor region (28) and / or of the second semiconductor region (24), forming at least one gate (Sla, 31b) on the first semiconductor region (28) and / or the second semiconductor region (24).
    [11" id="c-fr-0011]
    The method according to one of claims 7 to 9, wherein the method further comprises, after step b), steps of: - forming an insulating layer (63) on the first semiconductor block ( 18a) and on the second semiconductor block (18b), - bonding of the insulating layer (63) on a support (66), - removal of said substrate (1).
    [12" id="c-fr-0012]
    The method according to claim 11, wherein after forming the first block (18a) and the second semiconductor block (18b), the first semiconductor block (18a) and the second semiconductor block (18b) are covered. respectively a first semiconductor region (28) and a second semiconductor region (24), the method further comprising, after removal of the substrate (1) an etching of the first semiconductor block (18a) and the second semiconductor block (18b) so as to expose respectively the first semiconductor region (28) and the second semiconductor region (24).
    [13" id="c-fr-0013]
    The method of claim 12, wherein prior to forming the first semiconductor region (28), forming an etch stop layer on said first semiconductor block (18a), said stopping layer. etching being based on the first semiconductor material (5).
    [14" id="c-fr-0014]
    14. Method according to one of claims 11 to 13, wherein after having unveiled the first semiconductor region (28) and the second semiconductor region (24), forming one or more transistor gates (s) on the first semiconductor region (28) and the second semiconductor region (24).
    [15" id="c-fr-0015]
    15. Method according to one of claims 1 to 14, wherein after formation of said one or more first semiconductor blocks, forming on the first semiconductor block a stack comprising an alternation of bars based on a semi material. -conductor and the second semiconductor material.
    [16" id="c-fr-0016]
    The method according to one of claims 1 to 15, the method further comprising steps of: - forming an insulating mask (33) on the first semiconductor block (18a), the insulating mask comprising one or more holes respectively facing one or more first oblong semiconducting portion (s), - formation of semiconductor bars in said one or more holes, by growth of the second semiconductor material or of a given semiconductor material (25) having a different mesh parameter from that of the second semiconductor material (7).
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    同族专利:
    公开号 | 公开日
    US20170263495A1|2017-09-14|
    FR3048815B1|2019-05-10|
    US10665497B2|2020-05-26|
    引用文献:
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    2018-03-29| PLFP| Fee payment|Year of fee payment: 3 |
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1652112A|FR3048815B1|2016-03-14|2016-03-14|METHOD FOR CO-REALIZATION OF ZONES UNDER DIFFERENT UNIAXIAL CONSTRAINTS|
    FR1652112|2016-03-14|FR1652112A| FR3048815B1|2016-03-14|2016-03-14|METHOD FOR CO-REALIZATION OF ZONES UNDER DIFFERENT UNIAXIAL CONSTRAINTS|
    US15/457,447| US10665497B2|2016-03-14|2017-03-13|Method of manufacturing a structure having one or several strained semiconducting zones that may for transistor channel regions|
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